[P043]Abstract (Translated)

{
  "data": [
    {
      "pn": "US11205304B2",
      "title": "Memory device architectures and operation",
      "abstract": "Non- volatile memory devices (100, 610) logically organized to have erase blocks of at least two different sizes provide for concurrent erasure of multiple physical blocks (340) of memory cells (208, 308), while providing for individual selection of those physical blocks (340) for read and program operations, hi this manner, data expected to require frequent updating can be stored in locations corresponding to first erase blocks having a first size while data expected to require relatively infrequent updating can be stored in locations corresponding to second erase blocks larger than the first erase blocks.",
      "patent_id": "718ead9c-4f3c-4674-8f5a-24e126827269",
      "pn_related": "CN103106923A"
    }
  ],
  "status": true,
  "error_code": 0
}