[P044]Claim (Translated)

{
  "data": [
    {
      "pn": "US11205304B2",
      "claims": "1. A memory device (100, 610), which include:an array (104, 300) of non-volatile memory cells (208, 308) organized into a plurality of erasable physical blocks (340); andcircuitry (108, 110, 116) for controlling and/or accessing the array (104, 300) of non-volatile memory cells (208, 308);wherein said circuitry (108, 110, 116) for controlling and/or accessing is adapted to define a first logical erase block having a predetermined number of one or more physical blocks (340) and a predetermined number of two or the second logical erase block of more than two physical blocks (340);wherein the second logical erase block has a different number of physical blocks than the first logical erase block (340);andWherein the circuit is adapted to simultaneously select the two or more physical blocks of a second logical erase block during an erase operation.2. The memory device (100, 610) of claim 1, further include:wherein said circuitry (108, 110, 116) for controlling and/or accessing is further adapted to define a third logical erase block having a predetermined number of three or more physical blocks (340); andWherein the third logical erase block has a different number of physical blocks than both the first logical erase block and the second logical erase block (340).3. The memory device (100, 610) of claim 1, wherein one or more physical blocks (340) of the second logical erase block are selectable in response to more than one address signal.",
      "patent_id": "718ead9c-4f3c-4674-8f5a-24e126827269",
      "pn_related": "CN103106923A"
    }
  ],
  "status": true,
  "error_code": 0
}